1. Field of the Invention
The present invention relates to a despreading circuit of a receiver of a spread spectrum communication system such as mobile communication, radio LAN and the like, particularly to a simple despreading circuit which can reduce power consumption.
2. Description of the Related Art
In a spread spectrum communication system, in general, transmission data is narrow-band modulated (primary modulation) on a transmission side, and narrow-band modulated transmission data is further spread/modulated (secondary modulation), and the data subjected to the two-stage modulation is transmitted/outputted. Received data is despread on a reception side to extract the narrow-band modulated data, and a base band signal is regenerated in an ordinary wave detection circuit.
A conventional despreading circuit will be described with reference to FIG. 11. FIG. 11 is a block diagram of the conventional despreading circuit.
In the conventional despreading circuit, a sliding correlator constituted of a logic circuit is used, which performs capture in synchronization with a symbol break point and computes correlation in a synchronized phase.
Specifically, as shown in FIG. 11, the conventional sliding correlator is constituted of A/D converter 1, multiplier 2, PN code register 3, adder 4, and delay element 5.
Each section will be described hereinafter in detail. The A/D converter 1 receives a CDMA modulated analog signal, and converts the signal to a digital signal to output the signal.
The multiplier 2 multiplies and outputs PN code transmitted from the PN code register 3 and the signal transmitted from the A/D converter 1 for each chip.
The PN code register 3 transmits PN code (pseudo noise code) as a spread code to the multiplier 2.
Since one symbol is generally spread with a plurality of bits, the PN code has a multi-bit length, and the bit length is called the number of chips.
Additionally, a timing of PN code register 3 to output the PN code is based on an instruction from outside, and one bit is outputted every one chip time (obtained by dividing one symbol time by the number of chips).
The adder 4 adds and outputs signals transmitted from the delay element 5 and multiplier 2.
Moreover, the adder 4 transmits the added signal (correlation value) as a correlation output to the outside when one symbol time elapses after addition is started.
The delay element 5 delays the signal outputted by the adder 4 only by one chip time, returns it to the adder 4 and outputs it.
Specifically, the signal outputted by the multiplier 2 is accumulated/added over one symbol time by operation of adder 4 and delay element 5, so that the correlation output can be obtained after one symbol time elapses.
An operation of the conventional sliding correlator will next be described. The CDMA modulated analog signal is converted to a digital signal by the A/D converter 1, and multiplied by the PN code outputted by the PN code register 3 in the multiplier 2.
Subsequently, the adder 4 adds the signal outputted by the multiplier 2, and the signal returned from the delay element 5 over one symbol time to output the correlation output.
The correlation value for one symbol time is obtained as the correlation output in this manner.
Here, the synchronization phase can be detected as a point at which the correlation output reaches its peak, but when the sliding correlator is used, the correlation output cannot be obtained until one symbol time elapses. Therefore, the correlation output is obtained using each chip as a symbol start point, and the synchronization capture is attained in such a manner that the correlation output peaks. In general, it takes one symbol time multiplied by the number of chips to obtain the peak of the correlation output.
To solve the problem, a plurality of sliding correlators corresponding to the number of chips are arranged in parallel, and the correlation output is computed at a timing deviated by each chip in each sliding correlator. In this method, the synchronization capture is attained in a short time, but a circuit scale is impractically large.
On the other hand, in the conventional despreading circuit, as shown in FIG. 12, a matched filter may be used. FIG. 12 is a block diagram of the despreading circuit using the conventional matched filter.
As shown in FIG. 12, the matched filter is constituted of an A/D converter 11, sample hold circuit 12, multiplying means 13, PN code register 14, and adding means 15.
Each section will be described hereinafter in detail.
The A/D converter 11 receives a CDMA modulated analog signal, converts it to a digital signal of N bits, and outputs it, in the same manner as the A/D converter 1 in the sliding correlator.
Here, in consideration of signal precision, the A/D converter 11 preferably converts the analog signal to the digital signal of about six bits.
The sample hold circuit 12 is formed by connecting flip-flop circuits (D-FF) corresponding to the number of chips per one symbol in multiple stages. Each time the N bit signal is received from the A/D converter 11, the N bit signal transmitted from the previous D-FF is held. Moreover, the present held signal is successively transmitted to the next D-FF, and additionally transmitted to the multiplier 13.
Additionally, the first D-FF holds the N bit signal transmitted from the A/D converter 11, instead of the signal transmitted from the previous D-FF.
Specifically, the sample hold circuit 12 is provided with output terminals corresponding to the oversample multiple of the number of chips per one symbol to successively move the N bit signal transmitted from A/D converter 11 for each chip to the next output terminal and emit an output.
The multiplying means 13 is provided with a plurality of multipliers for the D-FFs of sample hold circuit 12 to multiply the N bit signal transmitted from each associated D-FF and the corresponding PN code transmitted from the PN code register 14 and output the N bit signal.
The PN code register 14 is the same as the PN code register 3 of the sliding correlator, except that the PN code for each chip is transmitted to the associated multiplier of the multiplying means 13.
As shown in FIG. 13, the adding means 15 is provided with a plurality of adders 20a to 20n to add the N bit signal transmitted from the multiplying means 13 and emit the correlation output of N bits. FIG. 13 is a block diagram of adding means 15.
As shown in FIG. 13, the adding means 15 is constituted of a plurality of adders 20 and an adder 23.
Moreover, each adder 20 is constituted of a plurality of adders 21, and flip-flop circuits (D-FF) 22 connected to the adders 21.
Specifically, a first adder 20a adds each two sets of a plurality of N bit signals transmitted from the multiplying means 13 by the adder 21, adjusts a timing by the D-FF 22, and outputs a set of the 1/2 number of N bit signals.
Specifically, as shown in FIGS. 12 and 13, when the number of chips per symbol is 256, the number of N bit signals outputted by the multiplying means 13 is 256 corresponding to the oversample multiple of the chips. Therefore, the number of N bit signals outputted by the first adder 20a is 128 corresponding to half of the oversample multiple of the chips.
Furthermore, a second adder 20b adds each two signals of a plurality of signals transmitted from the first adder 20a by the adder 21, adjusts the timing by D-FF 22, and outputs a set of the 1/2 number of N bit signals.
The set of a plurality of signals transmitted from the multiplying means 13 is successively added/synthesized by the adders 20a to 20n to reduce the signals by half. When two signals remain, the two signals are added by the adder 23 to transmit the correlation output to the outside.
An operation of the despreading circuit using the conventional matched filter will next be described.
The CDMA modulated analog signal is converted to the digital signal by the A/D converter 11, held for each sample by the sample hold circuit 12, successively fed rearward, and transmitted to the multiplying means 13.
Subsequently, the multiplying means 13 receives signal inputs corresponding to the number of samples, multiplies the inputs by the corresponding PN code transmitted from the PN code register 14, and emits an output.
Subsequently, the adding means 15 collectively adds/synthesizes the signals outputted by the multiplying means 13, and transmits the correlation output to the outside.
Additionally, the matched filter is broadly applied in the receiver of the spread spectrum communication, and the prior art regarding the matched filter is described, for example, in "Digital Matched Filter for Direct Spread Spectrum" of Japanese Patent Application Laid-open No. 107271/1997.
Moreover, the sliding correlator and matched filter for use in the spread spectrum communication are described in "Despreading Device and Receiver" of Japanese Patent Application Laid-open No. 68616/1999.
As described above, in the despreading circuit using the conventional sliding correlator, the number of gates is small, power consumption can be reduced, but much time is disadvantageously required from when the synchronization capture is attained until the correlation output is obtained.
Moreover, in the despreading circuit using the matched filter, since the correlation output is obtained for each phase, the time from when the synchronization capture is attained until the correlation output is obtained is short, but the number of gates is increased in accordance with the number of chips. Accordingly, the power consumption is disadvantageously increased.